The 5th Workshop on the Future of Computing Architectures (FOCA 2020) will be held on Friday October 30th, 2020 in a virtual format. This event is a full-day workshop that provides a forum for invited students in a broad range of fields covering all aspects of architectures for the future of computing. Invited students are expected to showcase their work and interact with their peers and members of the IBM Research community.

The topics covered by FOCA 2020 include but are not limited to:

  • Architectures for artificial intelligence / machine learning.
  • Security- and reliability-aware architectures.
  • Architectures for cloud, high-performance computing, and data centers.
  • Next-generation memory architectures.
  • Parallel architectures.
  • Power‐efficient architectures and systems.
  • Embedded, IoT, reconfigurable, and heterogeneous architectures.
  • Architectures for emerging technology and applications.
  • Quantum computing, quantum circuit optimization.

Past Editions


Organizing Committee

  • Augusto Vega
  • Karthik Swaminathan
  • Xinyu Que

Selection Committee

  • Alper Buyuktosunoglu
  • Anne Gattiker
  • Bishwaranjan Bhattacharjee
  • Bulent Abali
  • Charles Lefurgy
  • Hubertus Franke
  • Jeff Stuecheli
  • Jinjun Xiong
  • John-David Wellman
  • Kaoutar el Maghraoui
  • Leopold Grinberg
  • Manoj Kumar
  • Mihir Choudhury
  • Nagu Dhanwada
  • Nandhini Chandramoorthy
  • Ravi Nair
  • Sai Zeng
  • Sandhya Koteshwara
  • Swagath Venkataramani
  • Talia Gershon

Invited Speakers (Regular Presentations)

Lauren Biernacki

University of Michigan

Ghada Dessouky

Technical University of Darmstadt

Leila Delshadtehrani

Boston University

Thierry Tambe

Harvard University

Ashutosh Dhar

University of Illinois,

Daniel Richins

University of Texas,

Naorin Hossain

Princeton University


(all times are in Eastern Time)

Friday October 30th, 2020
8:50 - 9:00am Introduction and Welcoming Remarks
9:00 - 10:00am Keynote: "Future of Compute Accelerators in the Cloud"
Seetharami Seelam (IBM Research)
10:00 - 10:30am "HybCache: Hybrid Side-Channel-Resilient Caches for Trusted Execution Environments"
Ghada Dessouky (Technical University of Darmstadt)
10:30 - 10:45am Break
10:45 - 11:15am "Algorithms, Architectures and Prototypes for Accurate and Noise-Robust Speech and Natural Language
Processing Inference"
Thierry Tambe (Harvard University)
11:15 - 11:45am "AI Tax: The Hidden Cost of AI Data Center Applications"
Daniel Richins (University of Texas at Austin)
11:45am - 1:00pm Lunch Break
1:00 - 1:30pm "Can Hardware Enclaves Be as Powerful as Homomorphic Encryption?"
Lauren Biernacki (University of Michigan)
1:30 - 2:00pm "Towards Programmable Hardware Monitors for Security"
Leila Delshadtehrani (Boston University)
2:00 - 2:15pm Break
2:15 - 2:45pm "FReaC Cache: Folded-Logic Reconfigurable Computing in the Last Level Cache"
Ashutosh Dhar (University of Illinois at Urbana-Champaign)
2:45 - 3:15pm "TransForm: Formally Specifying Transistency Models and Synthesizing Enhanced Litmus Tests"
Naorin Hossain (Princeton University)
3:15 - 3:30pm Break
3:30 - 4:45pm Lightning talks:
• "Bit Error Robustness for Energy-Efficient DNN Accelerators"
   David Stutz (Max Planck Institute for Informatics, Germany)
• "Waferscale Processors: The Chiplet Approach"
   Saptadeep Pal (University of California, Los Angeles)
• "Symphony: A Framework for Intelligence Augmented Heterogenous Computing Systems"
   Subho Sankar Banerjee (University of Illinois at Urbana-Champaign)
• "Scalable Systolic Array Architecture (SSAA) — a General Convolutional Neural Network ISA and
   Compiler-Enabled Dataflow to Maximize Parallelism While Reducing Memory Utilization"
   Cesar Lopez-Carrasco (Texas A&M University)
• "LUTNet: Rethinking Inference in FPGA Soft Logic"
   Erwei Wang (Imperial College, London)
• "Mitigating Set-Conflict Based Cache Attacks with a Practical Fully-Associative Design"
   Gururaj Saileshwar (Georgia Institute of Technology)
• "A Low-Power, High-Throughput Microarchitecture for Long Short-Term Memory (LSTM) Neural Network Computation"
   Qianli Zhao (North Carolina State University)
• "Graph Analytics Accelerator Supporting Sparse Data Representation Using Crossbar Architectures"
   Nagadastagiri (Naga) Challapalle (Penn State University)
• "Compliance Aware Hybrid Scheduling"
   Nerla Jean-Louis (University of Illinois at Urbana-Champaign)

Open Q&A for lightning talks (30 mins)
4:45pm Concluding Remarks


Augusto Vega is a Research Staff Member at IBM T. J. Watson Research Center involved in research and development work in the areas of highly-reliable power-efficient embedded designs, cognitive systems and mobile computing. He holds M.S. and Ph.D. degrees from Polytechnic University of Catalonia (UPC), Spain.

Karthik Swaminathan is a Research Staff Member at IBM T. J. Watson Research Center. His research interests include power-aware architectures, domain-specific accelerators and emerging device technologies in processor design. He is also interested in architectures for approximate and cognitive computing, particularly in aspects related to their reliability and energy efficiency. He holds a Ph.D. degree from Penn State University.

Xinyu Que is a Research Staff Member in the Data Centric Systems Co-Design department at the T. J. Watson Research Center. He received his M.S. degree in Computer Science and Engineering from University of Connecticut and Ph.D. degrees in Computational Science and Software Engineering from Auburn University. Xinyu has broad interests in high performance computing and large-scale graph analytics.